Total 13 job vacancies by Renesas Electronics

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Location: Noida

Overview 
We are looking for a Sr Staff Engineer to support the Back End Physical Design aspects of high-performance compute SOC/MCU development. The candidate is expected to be hands-on and have intermediate level knowledge on advanced technology node back-end physical implementation, preferably with sign-off and tape-out experience in automotive grade SOCs.  

Responsibilities

• Contribute to advanced technology node physical implementation and sign-off domains. 
• Contribute to improve the process, methods and tools, driving the SOC chip development for lowest possible AUC (average unit cost) and highest yield quality  
• Contribute to Chip KPIs on Power, Performance, Area, Thermal & Schedule commitments are met predictably and consistently. 

Projects span a variety of business lines, and designs will need to meet a wide range of power / performance / area goals, depending on the product. Engagement and collaboration across global sites is a key aspect of this role as alignment of methods is essential and sharing of resources is common. Solid technical, communication, and consensus building skills and ability to influence solutions across a global organization will be required.
 

• Contribute to the Verification R&D team that is driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors. 
• Work closely with system architects and support define high level specifications that are implementable and robust.
• Interface with verification/validation teams to ensure design quality and robustness.
• Practice strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones
• Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips
• Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design,  and IP teams developing key technical networks to influence overall design improvements and verification methodologies
• Contribute driving best-in-class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI
• Participate in customer engagements assessing quality and risks

[ LOCATION : NOIDA ] / Sr Principal Engineer = Equivalent to a Director level role

Overview 

We are looking for a senior experienced leader to drive Chip assembly, define and implement infrastructure IP’s, define flow & methodology for high performance SOCs, to lead the overall front end design working very closely with system architects, SOC design architects, designers, software architects and information development teams. 
 

The successful candidate will be expected to  

• Contributes in a high-performance team to flawlessly integrate SoC’s with large number of IP’s. 
• Drives methodology to optimize integration flow and drive re-use across products. 
• Defines and drives infrastructure IP components essential for clock, power, reset and mode control. 
• Works with IP vendors and in house IP developers in coming up with realizable architecture  
• Review architecture documents and assess feasibility 
• Defines and implements power methodologies creating infrastructure and collaterals for downstream teams 
• Enables verification, emulation and physical Implementation teams  
• Reviews verification plans and assess weak area’s. 
• Key responsibility involves defining and implementing realizable bus architecture working closely with System & Chip architects 
• Works very closely with Application, IP & Information development teams creating best in experience customer facing documents. 

 [ Location : NOIDA ]

Be an integral member of a global, highly experienced team in R&D that drives the planning and execution of advanced microcontroller and microprocessors. 

As a Technical Program Manager your challenge will be to lead effective core teams with diverse technical leaders, helping them prioritize activities and communicate clearly while influencing peers and managers, and holding everyone accountable. You will drive strict project pace by accurately identifying technical risks for appropriate and timely closure. 

Your responsibilities 

• As a Technical Program Manager you are responsible for: 
• Leading all phases of SoC projects from architectural definition to validation 
• Creating project plans with milestones, timelines, ownership, and drive delivery 
• Facilitating project calls with global cross-functional teams to drive progress and resolve issues 
• Facilitating project health check awareness and support executive/senior management reporting 
• Acting as the first line of contact for issue escalation 
• Providing balance in technical support for architectural approvals, development, documentation closure and source control management (quality control) 
• Ensuring that the team is effectively delivering on their objectives and all the plans are on track. Perform risk analysis, identify and execute on mitigation steps 

[ LOCATION : NOIDA ] / Sr Principal Engineer = Equivalent to a Director level role

Responsibilities project scheduling, execution, and setting high-level technical vision. Projects span a variety of business lines, and designs will need to meet a wide range of power/performance/area goals, depending on the product. Engagement and collaboration across global sites is a key aspect of this role as alignment of methods is essential and sharing of resources is common. Strong technical, communication, and consensus building skills will be required as well as a demonstrated ability to influence solutions across a global organization. The ideal candidate will partner with local and global SoC teams to drive best practices with a target of productivity improvement. 

• Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors.  
• Work closely with system architects to define high level specifications that are implementable and robust. 
• Interface with verification/validation teams to ensure design quality and robustness. 
• Work with various EDA vendors to deploy next generation tools 
• Build strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones 
• Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips 
• Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design,  and IP teams developing key technical networks to influence overall design improvements and verification methodologies 
• Responsible for developing detailed Technical SoC verification execution plans, including resource schedules, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations 
• Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs. 
• Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI 
• Participate in customer engagements assessing quality and risks

Key Challenges: 

• This role requires close collaboration across global teams for resolving SoC Verification methodology alignment, the leadership role needs to be strongly integrated locally as well as globally in order to make the right trade-offs in methodology and project execution 
• This role with have direct impact on product execution for business lines, responsible for schedule, cost and quality commitments in SoC verification as well as identifying key improvements and ROI across the entire development process 
• Directors in IP development to plan strategic SoC Verification dependencies, roadmaps and methodologies and strategic IP innovations 
• Chief Architects and Engineers for developing SoC Verification strategic roadmaps and managing execution deliverables from SoC Verification team 
• Directors in implementation, RTL, DFT, Emulation to collaborate on project development plans and execution and develop common methodologies 
• VP’s and directors in R&D and Business Lines to provide project status, strategic methodologies and tools. 

Cross functional aspects: 

• Directors in IP development to plan strategic SoC Verification dependencies, roadmaps and methodologies and strategic IP innovations 
• Chief Architects and Engineers for developing SoC Verification strategic roadmaps and managing execution deliverables from SoC Verification team 
• Directors in implementation, RTL, DFT, Emulation to collaborate on project development plans and execution and develop common methodologies 
• VP’s and directors in R&D and Business Lines to provide project status, strategic methodologies and tools. 

[ Location: NOIDA ]

We are looking for an experienced leader for high performance SOCs/MCUs, for the SOC Architecture organization working closely with business, product marketing, system architects, SOC design architects and designers, software architects and developers.

Responsibilities
The successful candidate will be expected to 

• Drive Architecture that will define the SOC/MCU architecture and detailed technical specifications from product requirements provided by business and product marketing organizations.
• Define-Own-Deliver the chip implementation that meet KPI & product requirement, including the specification compliance – ensuring coverage from verification, validation, characterization and test. Then reviewing the outcomes to make sure the product is compliant.
• Experience leading advanced automotive high performance SOCs/vehicle computers/SDVs/MCUs highly desired.
• Drive paradigm shifts in SOC/MCU execution including team structures, tool usage, methods, processes for high quality tape-out.
• IP selection and make/buy decisions are a key factor for this role.
• Need to work with peers across the business to drive change throughout Renesas to have common methods that work across the whole organization in partnership and collaboration with stakeholders and influence the direction taken.
• Role will involve external stakeholder engagement such as: supplier management, technical conference participation, technical standards engagement/awareness.
• Involve training program definition and roll out, lessons learned proliferation and best practice sharing.

[ Location: NOIDA ]

We are looking for a senior technical leader to drive the Back End Physical Design aspects of high-performance compute SOC/MCU development. The candidate must be highly experienced, hands-on and have expert level knowledge on advance technology node back-end physical implementation, SOC convergence, sign-off and tape-out experience on automotive grade SOCs.

Responsibilities
The successful candidate will be expected to 

• Be the focal point and drive the global teams on advance technology node physical implementation and sign-off domains.
• Continuously improve the process, methods and tools, driving the SOC chip development for lowest possible AUC (average unit cost) and highest yield quality 
• Drive chip implementation and sign-off activities
• Ensure Chip KPIs on Power, Performance, Area, Thermal & Schedule commitments are met predictably and consistently.
• Work closely with Design Enablement, SOC architecture/design, Package, Post-Silicon test teams and Foundry partners to meet the NPI and technology entitlement.

Need to work with peers across the business to drive change throughout Renesas to have common methods that work across the whole organization in partnership and collaboration with stakeholders and influence the direction taken.

[ Job Location: NOIDA ]

Responsibilities include resource management, project scheduling, execution, and setting high-level technical vision. Projects span a variety of business lines, and designs will need to meet a wide range of power/performance/area goals, depending on the product. Engagement and collaboration across global sites is a key aspect of this role as alignment of methods is essential and sharing of resources is common. Strong technical, communication, and consensus building skills will be required as well as a demonstrated ability to influence solutions across a global organization. The ideal candidate will partner with local and global SoC teams to drive best practices with a target of productivity improvement.

• Lead Soc RTL and Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors. 
• In this role you will also lead and build this high performance SoC Verification team, including training and mentoring NCG’s and developing next level verification leads
• Fully own RTL delivery for a multitude of projects
• In this role you will also lead and build this high performance SoC RTL and Verification team, including training and mentoring NCG’s and developing next level verification leads
• Responsible for developing team members goals and development plans ensuring a high performing SoC verification team
• Work closely with system architects to define high level specifications that are implementable and robust.
• Interface with verification/validation teams to ensure design quality and robustness.
• Work with various EDA vendors to deploy next generation tools
• Build strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones
• Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips
• Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design,  and IP teams developing key technical networks to influence overall design improvements and verification methodologies
• Responsible for developing detailed Technical SoC verification execution plans, including resource schedules, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations
• Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs.
• Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI
• Participate in customer engagements assessing quality and risks

Key Challenges:

• This role requires close collaboration across global teams for resolving SoC Verification methodology alignment, the leadership role needs to be strongly integrated locally as well as globally in order to make the right trade-offs in methodology and project execution
• This role with have direct impact on product execution for business lines, responsible for schedule, cost and quality commitments in SoC verification as well as identifying key improvements and ROI across the entire development process

Cross functional aspects:

• VP and Directors in IP development to plan strategic SoC Verification dependencies, roadmaps and methodologies and strategic IP innovations
• Chief Architects and Engineers for developing SoC Verification strategic roadmaps and managing execution deliverables from SoC Verification team
• Directors in implementation, RTL, DFT, Emulation to collaborate on project development plans and execution and develop common methodologies
• VP’s and directors in R&D and Business Lines to provide project status, strategic methodologies and tools.

Level: Director/Sr Principal Engr

We are looking for an experienced leader for high performance SOCs/MCUs, for the SOC Architecture organization working closely with business, product marketing, system architects, SOC design architects and designers, software architects and developers.

Responsibilities
The successful candidate will be expected to 

• Drive Architecture that will define the SOC/MCU architecture and detailed technical specifications from product requirements provided by business and product marketing organizations.
• Define-Own-Deliver the chip implementation that meet KPI & product requirement, including the specification compliance – ensuring coverage from verification, validation, characterization and test. Then reviewing the outcomes to make sure the product is compliant.
• Experience leading advanced automotive high performance SOCs/vehicle computers/SDVs/MCUs highly desired.
• Drive paradigm shifts in SOC/MCU execution including team structures, tool usage, methods, processes for high quality tape-out.
• IP selection and make/buy decisions are a key factor for this role.
• Need to work with peers across the business to drive change throughout Renesas to have common methods that work across the whole organization in partnership and collaboration with stakeholders and influence the direction taken.
• Role will involve external stakeholder engagement such as: supplier management, technical conference participation, technical standards engagement/awareness.
• Involve training program definition and roll out, lessons learned proliferation and best practice sharing.

Level: Director/Sr Principal Engr

We are looking for an experienced leader for high performance SOCs/MCUs, for the SOC Architecture organization working closely with business, product marketing, system architects, SOC design architects and designers, software architects and developers.

Responsibilities
The successful candidate will be expected to 

• Drive Architecture that will define the SOC/MCU architecture and detailed technical specifications from product requirements provided by business and product marketing organizations.
• Define-Own-Deliver the chip implementation that meet KPI & product requirement, including the specification compliance – ensuring coverage from verification, validation, characterization and test. Then reviewing the outcomes to make sure the product is compliant.
• Experience leading advanced automotive high performance SOCs/vehicle computers/SDVs/MCUs highly desired.
• Drive paradigm shifts in SOC/MCU execution including team structures, tool usage, methods, processes for high quality tape-out.
• IP selection and make/buy decisions are a key factor for this role.
• Need to work with peers across the business to drive change throughout Renesas to have common methods that work across the whole organization in partnership and collaboration with stakeholders and influence the direction taken.
• Role will involve external stakeholder engagement such as: supplier management, technical conference participation, technical standards engagement/awareness.
• Involve training program definition and roll out, lessons learned proliferation and best practice sharing.

We are looking for an experienced leader for high performance SOCs & MCUs, to lead end to end design execution, working closely with Architects, Functional leads, Business leads and program management.

Responsibilities
The successful candidate will be expected to 

• Lead the Automotive & Consumer SOC design execution meeting the PPA requirements and architecture intent.
• Engages from SoC Definition to Productization
• Drive and direct SOC & MCU vertical Chip development and silicon design teams in ensuring predictable; on-schedule; high quality; first-time-right executions working in close alignment with business/customer, product marketing, program management, manufacturing team, Software, FuSa & security .
• Deliver chip implementation that meet KPI & product requirement, including the specification compliance – ensuring coverage from verification, validation, characterization and test.
• Optimize design and design process cutting across functional boundaries.
• Participate 7in Make vs buy assessment and IP selection.
• Participate in technology node selection.
• Summarize and report progress and risks to higher management
• Need to work with peers across the business to drive change throughout Renesas to have common methods that work across the whole organization in partnership and collaboration with stakeholders and influence the direction taken.
• Role will involve external stakeholder engagement such as: supplier management, technical conference participation, technical standards engagement/awareness.
• Involve training program definition and roll out, lessons learned proliferation and best practice sharing.

We are looking for a senior experienced leader to drive Chip assembly, define and implement infrastructure IP’s, define flow & methodology for high performance SOCs, to lead the overall front end design working very closely with system architects, SOC design architects, designers, software architects and information development teams.

Responsibilities
The successful candidate will be expected to 

• Build a high-performance team to flawlessly integrate SoC’s with large number of IP’s.
• Drive methodology to optimize integration flow and drive re-use across products.
• Define and drives infrastructure IP components essential for clock, power, reset and mode control.
• Work with IP vendors and in house IP developers in coming up with realizable architecture
• Review architecture documents and assess feasibility
• Define and implements power methodologies creating infrastructure and collaterals for downstream teams
• Enable verification, emulation and physical Implementation teams
• Review verification plans and assess weak area’s.
• Key responsibility involves defining and implementing realizable bus architecture working closely with System & Chip architects
• Work very closely with Application, IP & Information development teams creating best in experience customer facing documents.
• Mentor and groom team.