Total 230 job vacancies by Renesas Electronics

'SoCバックエンド設計業務の設計エンジニアまたは設計リーダー。自動レイアウト設計、物理レイアウト設計の技術開発、製品適用。
・自動レイアウト設計：
　市販レイアウトツールを用いたフロアプラン作成、タイミング考慮の配置＆配線
・物理レイアウト設計：
　電気特性を理解した上でIO配置、アナログマクロ配置、電源設計、及び物理/電源検証

★自動レイアウト設計、物理レイアウト設計いずれの場合も、海外拠点と協業

※就業場所の変更の範囲、従事すべき業務の変更の範囲については、選考時に詳細をお伝えいたします。

Overview 

We are seeking a talented and motivated Hardware Architect (AI Sub-system) to join our R&D team to own, define, and drive exploration and design of the next generation hardware for AI sub-system in high performance computing (HPC) SoCs.

Our division’s mission is to use the latest AI and cloud technologies to develop the best AI inference for advanced driver safety engineers building self-driving vehicles and other high performance compute products. Renesas is the leading automotive electronics supplier globally, and this is a rare opportunity to develop the infrastructure required to deploy our AI software to the billions of devices we ship to customers every year. You will join our newly formed AI & Cloud Engineering organization of around 100 software engineers. Due to strong demand for our AI-related products we are planning to triple in size in the next three years, so there is lots of room for you to help us grow the team together while remaining small. Our team’s key locations are Tokyo, London, Paris, Dusseldorf, Beijing, Singapore, Ho Chi Minh City, and other metropolitan areas, but you can also join fully remotely from other locations globally or get our support to relocate to our key hubs such as Tokyo.  

Responsibilities  

1. Participate and lead in the architecture design of next generation multi-core AI sub-system including CPU/DSP/NPU, memory hierarchies, scalable interconnects, etc.
2. Perform HW/SoC architectural modeling, performance analysis, trade-off analysis, PPA optimization, etc.
3. Deliver architecture specifications to design teams and articulate them effectively across stakeholders ranging from system and software teams to architecture peers, and to technology leadership.
4. Collaborate with silicon and platform bring-up to verify and debug the AI sub-system and its delivered performance.

Location: Noida

Overview 
We are looking for a Sr Staff Engineer to support the Back End Physical Design aspects of high-performance compute SOC/MCU development. The candidate is expected to be hands-on and have intermediate level knowledge on advanced technology node back-end physical implementation, preferably with sign-off and tape-out experience in automotive grade SOCs.  

Responsibilities

• Contribute to advanced technology node physical implementation and sign-off domains. 
• Contribute to improve the process, methods and tools, driving the SOC chip development for lowest possible AUC (average unit cost) and highest yield quality  
• Contribute to Chip KPIs on Power, Performance, Area, Thermal & Schedule commitments are met predictably and consistently. 

Projects span a variety of business lines, and designs will need to meet a wide range of power / performance / area goals, depending on the product. Engagement and collaboration across global sites is a key aspect of this role as alignment of methods is essential and sharing of resources is common. Solid technical, communication, and consensus building skills and ability to influence solutions across a global organization will be required.
 

• Contribute to the Verification R&D team that is driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors. 
• Work closely with system architects and support define high level specifications that are implementable and robust.
• Interface with verification/validation teams to ensure design quality and robustness.
• Practice strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones
• Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips
• Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design,  and IP teams developing key technical networks to influence overall design improvements and verification methodologies
• Contribute driving best-in-class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI
• Participate in customer engagements assessing quality and risks

Work you’ll do:

As a Campus Program Manager, you will assist in the development and implementation of the Campus Recruiting Strategy & Execution. Provide direction, support, and guidance to their assigned recruiting team. Ensure the collective local and vital strategic university campus recruiting programs are established and implemented to enable the team to hire the quality and quantity of graduate and undergraduate candidates set by firm and national leadership.

Job Responsibilities:

• Helping the team to initiate and build relationships with campuses.
• Monitoring & managing entire recruiting life cycle at university.
• Partner with multiple internal and external team members to drive workforce development strategy.
• Understand Global Strategy towards University engagement & recruiting.
• Continuously review and evaluate technology tools to enhance internal University hiring processes and improve candidate experience.
• Assisting the team in effectively planning and conducting the recruiting events
• Development and alignment of processes with respect to student identification, interviewing, and selection ensuring excellent candidate experience.
• Design diversity hiring programs in universities in partnership with the diversity, equality, and inclusion team to expand the diverse talent pool.
• Provide subject matter advice & recommendations to business Leaders and develop methodologies for hiring and retaining graduates.
• Developing and executing presentations, career fairs and participating in campus interviews
• Broad knowledge of regional leadership, business/market opportunities, and recruiting challenges is highly desirable.

1. Responsibilities: 

i. as project leader in creating product definition with marketing and applications 

ii. Apply your in-depth understanding of power process technologies, both existing and those under development, to design innovative power management & gate driver products. 

iii. Transistor level design of mixed-signal circuits of new and derivative power management products 

iv. To validate circuit and system performance in the lab. 

1. Responsibilities: 

i. as project leader in creating product definition with marketing and applications 

ii. Apply your in-depth understanding of power process technologies, both existing and those under development, to design innovative power management & gate driver products. 

iii. Transistor level design of mixed-signal circuits of new and derivative power management products 

iv. To validate circuit and system performance in the lab. 

Job Responsibilities:

1. Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.
2. Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.
3. Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
4. Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
5. Where possible, use schematic driven layout and consider top level auto routing.
6.  Involve in review session and prepare all related document and data preparation for wafer tape out.

Job Responsibilities:

1. Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.
2. Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.
3. Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
4. Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
5. Where possible, use schematic driven layout and consider top level auto routing.
6.  Involve in review session and prepare all related document and data preparation for wafer tape out.

ISO 26262対応が求められる車載向け半導体製品（MCU, SoC, A&P製品）向けの機能安全要件策定、管理をリード頂きます。グローバルなメンバーと一緒に働ける職場になります。
①マーケティング部門、また製品設計部門と協調した次世代製品の機能安全要件定義、競合他社分析、及び管理
②リーディング顧客からの要求に対する回答作成
③複数のルネサス製品を組み合わせたシステムの機能安全コンセプト策定、管理
④機能安全要件のデータベース化策定、管理

In your daily work you will handle the following activities: 
●    Develop necessary hardware and software to enable comprehensive silicon device evaluation: PCB schematic and layout design, automation software
●    Conduct power IC evaluations and debugging on chip and board level
●    Create technical documents (datasheet, evaluation report, application note)
●    Plan and lead device evaluation, develop manual and automated bench test methods 
●    Document errata to support necessary device modifications 
●    Support internal design engineers, FAEs, and external customers to solve technical issues
●    Work with technical marketing, system architect, and design engineers to define IC functions and specifications
●    Provide first line technical support and reports during customer design phase
●    Work with Quality, Test, and Product engineers for device testing and qualification

*The full details regarding your position scope as well as any future potential changes in work location and job scope will be provided during the interview process.

• Design and develop Chip, IP and CPU by hardware description language (HDL) 
• Investigate and verify system specification by high level language (C or C-like modelling)
• Apply advanced hardware design methodology (especilay, Layout, timing closure and DFT) to IP, CPU and Chip design.
• Evaluate and test prototype on FPGA

・パワーモジュール内部の配線などの電気回路設計
・SiCの並列駆動における発振抑制
・パワーモジュール電磁気回路シミュレーション技術開発（MBD）
・ゲートドライバ設計チームとの連携によるKIT開発
・パワーモジュールの静特性・動特性など電気特性評価
・パワーモジュール回路設計課のマネージメント

・パワーモジュールの信頼性構造設計
・パワーモジュールの不良解析
・パワーモジュールの寿命推定（MBD）
・パワーモジュール熱応力シミュレーション技術開発
・品質保証チームとの連携による信頼性評価試験取りまとめ

Develop u-boot/BSP drivers on FreeRTOS / Renesas Flexible Software Package.
    - Develop OpenAMP for Inter-Processor Communication between Linux running on Cortex Arm core and FreeRTOS running on Cortex Realtime core.
    - Develop Proof of Concept to demonstrate functions and performance.
    - Verify solution package
    - Conduct world wide customers support (Asia, Europe, America)