Total 126 communications engineer job vacancies in Art / Design / Entertainment category in D05 Clementi New Town, Hong Leong Garden, Pasir Panjang

Job Description & Requirements

1) Modelling and form finding of tensile membrane structure

2) Engineering Analysis Using Windas Work Station

3) Preparation of engineering report

4) CFD Simulation (Wind, Rain, Thermal Confort)

5) Project management, liase with clients, architects and factory

6) Bill of quantity preparation

7) Software Development

Job Scope:

• Carry out structural design and produce professional engineering calculation complying to Eurocodes and prevailing building control regulations
• Attending technical meetings with authorities, developer, and contractors
• Prepare technical engineering reports as and when required by authorities or clients

Requirements:

Minimum Degree (Civil/ Structural Engineering) in recognised University

• Minimum 1 or 2 years of experience as Design Engineer in building construction
• Willing to and with enthusiasm to learn in the field of civil & structural engineering design
• Knowledge with 3D Softwares is an added advantage

Responsibilities:

• Perform Printed Circuit Board (PCB) design from Schematic, Layout to Gerber for design and development of consumer electronic products
• Consolidate Bill of Materials for manufacturing and assembly
• Other Ad-hoc daily tasks

Requirements:

• Degree/Diploma in Electronics Engineering related to PCB
• Minimum of 3 years’ experience in PCB design using Cadence Allegro tools
• Equivalent experience using other PCB CAD tools will be considered
• Good knowledge of electronic products will be an added advantage
• Able to work independently as well as a team-player

Position Overview:

The Staff/Senior Design Engineer will be responsible for developing micro-architecture for Image Signal Processing Unit (ISP) and Computer Vision Unit (CV) related algorithms. They will utilize RTL design using Verilog/System Verilog coding and High-Level Synthesis (HLS) tools like Catapult. Additionally, they will analyse metrics such as power, performance, and area to meet key objectives and results. Collaboration with architects and verifiers to drive verification signoff efficiently, as well as support for FPGA tasks such as emulation, validation, and debugging, are also key aspects of the role.

Job Descriptions:

• Develop Micro-Architecture:Create micro-architecture for ISP and CV related algorithms.
• RTL Design: Utilize Verilog/System Verilog coding and HLS tools (Catapult) for RTL design.
• Metrics Analysis: Measure and analyze metrics like power, performance, and area to achieve objectives.
• Verification Support: Collaborate with architects and verifiers to drive verification signoff efficiently.
• FPGA Support: Assist with FPGA tasks including emulation, validation, and debugging.

Job Requirements:

• Education: Master’s degree or above in Electrical/Electronics/Computer Engineering is required.
• Experience: Minimum of 3 years of experience in ASIC design is required. Prior experience with image signal processing courses or projects is beneficial. Candidates with expertise in ASIC frontend design phases, including RTL design using Verilog/System Verilog and familiarity with relevant EDA tools and CAD flows, are preferred.
• Technical Skills:

o Proficiency in HDL languages (Verilog, System Verilog) is essential.

o Knowledge of all phases of ASIC frontend design and sign-off is required.

o Experience in image/vision/video data processing or algorithm acceleration.

o Familiarity with scripting languages like Python, Perl, or C/C++ is a plus.

o Soft Skills: Excellent teamwork and communication skills are essential for collaborating effectively with architects, verifiers, and other team members.

• Additional Notes:

o Strong analytical skills are necessary to measure and analyze metrics such as power, performance, and area.

o This role requires a deep understanding of micro-architecture development for image signal processing and computer vision algorithms.

o Candidates should be able to work efficiently and independently, as well as within cross-functional teams, to achieve project goals.

Job Description:

- Perform Civil, Structural Analysis and Design (entry-level) to meet project specifications

- Coordination and Liaise with Clients, Authority and Other Consultants, Contractors on Projects

- Ensuring Good Project Documentation and Submission to Authority and Clients

- Attend Project Meeting and Perform Inspections on Designed Works

- Reporting to Senior Engineer

Job Requirements:

- Candidate must possess at least a Bachelor's Degree / Post-Graduate Diploma / Professional Degree in Engineering (Civil/ Structural) or equivalent, recognized by Professional Engineering Board of Singapore

- At least 1 Year (s) of working experience in the related field is required for this position

- Good Working Attitude, Self-Motivated, Positive Thinking, Independent, Discipline, Attention to Details and Ownership of Tasks

- Familiar with Local Design Standard and Code

- Knowledge of Design Software, e.g., STAAD Pro, Plaxis, AutoCAD will be added advantage

- Candidate with longer experience or qualifications will be considered for Senior Positions

Responsibilities:

• RTL-level digital design and problem solving
• Function verification and support
• Digital synthesis, place-and-route, Design for Test and Static timing analysis
• Digital functional verification and FPGA verification

Requirements:

• Bachelor/Masters in Electronics/Electrical Engineering with Mixed Signal IC design/verification experience.
• Strong written and verbal communication skills.
• Strong coding and documentation practices.
• Fluent in Verilog coding, design, simulation, and verification domains.
• Team player
• Definition and implementation of custom digital interfaces (I2C, 3-wire, single_wire etc.).
• Definition and implementation of custom finite state machines, register maps, control logic which interface with analog circuits such as linear regulators and drivers and proprietary IPs like OTP or flash memory
• RTL design for synchronous and asynchronous applications, including multiple clock domains
• Logic synthesis, place & route, static timing analysis, logic equivalency checking
• Usage of Cadence tools like Incisive Enterprise Simulator, SimVision, Genus, First Encounter, Conformal, Modus, Tempus and Virtuoso will be preferred
• Applicants with more than 5 years of relevant experience will be considered for the position of Senior Digital IC designer.

Responsibilities:

• RTL-level digital design and problem solving
• Function verification and support
• Digital synthesis, place-and-route, Design for Test and Static timing analysis
• Digital functional verification and FPGA verification

Requirements:

• Bachelor/Masters in Electronics/Electrical Engineering with Mixed Signal IC design/verification experience.
• Strong written and verbal communication skills.
• Strong coding and documentation practices.
• Fluent in Verilog coding, design, simulation, and verification domains.
• Team player
• Definition and implementation of custom digital interfaces (I2C, 3-wire, single_wire etc.).
• Definition and implementation of custom finite state machines, register maps, control logic which interface with analog circuits such as linear regulators and drivers and proprietary IPs like OTP or flash memory
• RTL design for synchronous and asynchronous applications, including multiple clock domains
• Logic synthesis, place & route, static timing analysis, logic equivalency checking
• Usage of Cadence tools like Incisive Enterprise Simulator, SimVision, Genus, First Encounter, Conformal, Modus, Tempus and Virtuoso will be preferred
• Applicants with more than 5 years of relevant experience will be considered for the position of Senior Digital IC designer.

Responsibilities:

• The Mixed-Signal IC (MEMS Interface) Design Engineer will be responsible for the design and development of capacitive and/or piezoelectric MEMS interface ASICs, including the required amplifiers, ADCs, filters and control logic, with characteristic high impedance inputs, ultra low power, low noise circuits etc .
• The responsibility of the Mixed-Signal IC Design Engineer includes scheduling, design, simulation and layout of mixed-signal circuit blocks, including pre- and post-silicon verification.
• It is also expected that you will conduct periodic design reviews, including with application engineers.
• It is also expected that you will support test development and product development teams in bringing projects to production.

Requirements:

• PhD/Master’s Degree in Electronics/Electrical Engineering.
• Minimum 6 years’ experience in Analog or Mixed-signal IC design.
• Very good knowledge of CMOS processes.
• Highly proficient in analog and mixed-signal IC design EDA tools.
• Experienced in analog and mixed-signal circuit designs, such as regulators, DC-DC converters, low-power, low-noise biasing circuits and amplifiers, sigma-delta modulation and ADCs, etc
• Experience in design of high resolution, low power sigma-delta modulation preferred.
• Experience in design of ultra low power ADC preferred.
• Skilled in laboratory testing of IC prototypes.
• Knowledge of Linux operating system required.
• Experience in MEMS interface ASIC design advantageous.

Responsibilities:

• Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips.
• Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff
• Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block owners.
• TOP role for the complicated hierarchical chip (more than 20 Million instances plus 500+ macros), doing floorplan and partition, responsible for full chip tapeout

Requirements:

• Bachelor/Master Degree in Electrical/Computer Engineer.
• Experience in physical design with tape-outs.
• Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC2 or Innovus.
• Good in script programming with Perl, TCL/TK or other languages.

Interested candidate kindly forward your *Updated resume (word doc format) to ronnie.tiew@alpsoft-tech.com

Job Title: Marine structure engineer ID9024
Location: Beach Road
Working Hours:
Working Hour: Mon to Fri;9am-6pm
Salary: $3500-$5000
Benefit:
*13-month salary
*AL 21 days

Job Description:
•Involved in the design of infrastructure type of works (mostly Marine related).
•Structural Design and analysis (reinforced concrete, steel design, ship-shore design)
•Coordinate and review drafting work
•Marine engineering (ship-shore interface design, design of berthing and mooring equipment, determine environmental loads on port structures like breakwaters, jetties, quay walls and offshore foundations
•Other ad-hoc duties as assigned

Requirement:
•Minimum degree in Marine Engineering
•Fresh graduate are welcome to apply

Responsibilities:

• Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips.
• Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff
• Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block owners.
• TOP role for the complicated hierarchical chip (more than 20 Million instances plus 500+ macros), doing floorplan and partition, responsible for full chip tapeout

Requirements:

• Bachelor/Master Degree in Electrical/Computer Engineer.
• Experience in physical design with tape-outs.
• Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC2 or Innovus.
• Good in script programming with Perl, TCL/TK or other languages.

Job Description:

- Perform Civil, Structural Analysis and Design (entry-level) to meet project specifications

- Coordination and Liaise with Clients, Authority and Other Consultants, Contractors on Projects

- Ensuring Good Project Documentation and Submission to Authority and Clients

- Attend Project Meeting and Perform Inspections on Designed Works

- Reporting to Senior Engineer

Job Requirements:

- Candidate must possess at least a Bachelor's Degree / Post-Graduate Diploma / Professional Degree in Engineering (Civil/ Structural) or equivalent, recognized by Professional Engineering Board of Singapore

- At least 1 Year (s) of working experience in the related field is required for this position

- Good Working Attitude, Self-Motivated, Positive Thinking, Independent, Discipline, Attention to Details and Ownership of Tasks

- Familiar with Local Design Standard and Code

- Knowledge of Design Software, e.g., STAAD Pro, Plaxis, AutoCAD will be added advantage

- Candidate with longer experience or qualifications will be considered for Senior Positions

The position is an exciting opportunity to be part of a flexible and dynamic team in the growing markets of mixed signal chips with signal processing IPs, ARM processor and AMBA bus interface like Wireless Chargers, Bluetooth, PMIC etc. used in Mobile, Tablets, Microcontrollers etc. The role works within the digital design team with the aim to create an efficient Digital Design.

Responsibilities and Duties include but not limited to:

• Work at IP level design, but occasionally also at SOC design.
• Creation of RTL code
• Some opportunities to integrate the IP in the SOC
• UPF flow, Low power Flow, Power aware simulations
• CDC/RDC/LINT checks using various tools
• Verification of concept using Matlab/Simulink and toolboxes
• Synthesis, Scan insertion, ATPG.
• STA.
• Schedule preparation at IP level together with the Design leader and execution adhere to plan.
• Reporting to the management.
• Accountability.

Qualification Requirements:

• Masters in Electronics' Engineering (a relevant experience with minimum 2 years in a semiconductor or high technology R&D environment would be appreciated)
• Some Knowledge/Experience/Exposure as below would be appreciated:

1. ARM based Architectures, AMBA bus, Peripherals, Boot
2. RISC-V architectures
3. Hardware Design Language (such as VHDL or Verilog)
4. CDC, RDC, LINT
5. Synthesis, Scan Insertion, ATPG
6. Physical Design, including Power analysis, Clock tree Synthesis, Power Gating, Physical Checks
7. Power Aware, Low power and UPF methodology
8. Tools porting from Verilog RTL into C++
9. Scripting languages (PERL, TCL, PYTHON)
10. Knowledge in Static Timing Analysis

• Able to work in a multi-cultural team.
• Strong analytical and problem-solving skill.
• Able to keep up with fast moving new design methodology.
• Candidates with extensive experiences will be considered as Staff Engineers/Design Managers
• Salary package will be offered base on working experience

• Liaise with Clients, Architects & Builders.
• Recognized Degree in Civil and Structural Engineering.
• Minimum 5-8 years experience in structural design.
• Familiar with reinforced concrete and steel design.
• Responsible for design and checking of drawings.
• Coordination of project submission to authorities and construction.
• Must be willingly to work on construction sites (dusty & dirty environment), long hours and Sundays/Public Holidays (if required)
• Salary will commensurate base on qualification and experience

All candidates welcome to apply

Be part of a team in creating state-of-the-art Secure Low Power SoC ARM-based SoC/MCU for the Low-End , Mid and High-End performance MCU product line in a IC Design Environment.

Responsible:

• Engage design team and architects to strategies DFT Test plan for SoC top level
• Create DFT test modes, scan architecture, clocking and reset architecture.
• Plan Pin-Muxing and Pad and Boundary scan (BSDL) generation
• Execute JTAG TAP network generation and verification.
• Quality check with Spyglass analysis for scan using spyglass tool
• Execute Scan insertion using DC / Tessent tools
• Deploy Scan constraints development for Atspeed, shift and slow capture mode.
• Generate ATPG pattern generation using synopsys Tetramax tools
• Analyze and report on test coverage metrics to ensure comprehensive testing of designs.
• Implement improvements to enhance test coverage and efficiency.
• Verify No-timing and SDF simulation of ATPG patterns using VCS and NCSim tools
• Implement MBIST MBIST repair and verification using Mentor Graphic Tessent tools.
• Boundary scan verification
• Generate STIL test patterns for tester
• Silicon bring-up and failure debug

Requirements:

• Requires BSc/MSc or PhD in electrical and electronic or Computer engineering
• Requires > 5 years or more of experience in DFT at IP and SoC top level. Proficient at using DC ,tetramax and MG tessent DFT tools
• Tape-out at least 5 chips and tested to pass on tester.
• Requires strong understanding of state of the DFT methodology , flat and hierarchical implement of DFT from IP to SoC top.
• Capable of understanding UPF to enable multiple power domain verification
• Capable of leading, review and guiding younger DFT engineers in their daily tasks
• Able to work in a team with a strong drive to excel
• Able to work independently on a given assignment and work hard to finish on time
• Good written and communication skills